1. Technical Field of the Invention
This invention relates generally to programmable logic systems and more particularly to pin arrangements for programmable logic systems.
2. Description of Related Art
Communication systems and other modern programmable logic systems are known to process and/or transport large amounts of data between a plurality of end circuit components, user devices, which, for example, include telephones, facsimile machines, computers, television sets, cellular telephones, personal digital assistants, etc. For example, a programmable logic device within a communication system may be required to produce significant amounts of data and control signals to a plurality of circuit elements to facilitate communications. As is also known, such communication systems may be local area networks (LANs) and/or wide area networks (WANs) that are stand-alone communication systems or interconnected to other LANs and/or WANs as part of a public switched telephone network (PSTN), packet switched data network (PSDN), integrated service digital network (ISDN), or Internet whose function is largely to process or transceive large amounts of data. As is further known, communication systems include a plurality of system equipment to facilitate the transporting of data. Such system equipment includes, but is not limited to, routers, switches, bridges, gateways, protocol converters, frame relays, private branch exchanges, etc.
The transportation of data within communication systems is governed by one or more standards that ensure the integrity of data conveyances and fairness of access for data conveyances. For example, there are a variety of Ethernet standards that govern serial transmissions within a communication system at data rates of 10 megabits per second, 100 megabits per second, 1 gigabit per second and beyond. Synchronous Optical NETwork (SONET), for example, requires 10 gigabits per second. In accordance with such standards, many system components and end user devices of a communication system transport data via serial transmission paths. Internally, however, the system components and end user devices process data in a parallel manner. As such, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information.
As the demand for data throughput increases, so do the demands on high-speed serial transceivers, as well as corresponding processing logic. The increased throughput demands are pushing some current integrated circuit manufacturing processes to their operating limits, where integrated circuit processing limits (e.g., device parasitics, trace sizes, propagation delays, device sizes, etc.) and integrated circuit (IC) fabrication limits (e.g., IC layout, frequency response of the packaging, frequency response of bonding wires, etc.) limit the speed at which the high-speed serial transceiver may operate without excessive jitter performance and/or noise performance.
A further alternative for high-speed serial transceivers is to use an IC technology that inherently provides for greater speeds. For instance, switching from a CMOS process to a silicon germanium or gallium arsenide process would allow integrated circuit transceivers to operate at greater speeds, but at substantially increased manufacturing costs. CMOS is more cost effective and provides easier system integration. Currently, for most commercial-grade applications, including communication systems, such alternate integrated circuit fabrication processes are too cost prohibitive for wide spread use.
As data processing requirements increase for any purpose including communications as described above, application specific integrated circuits (ASIC), programmable logic devices such as field programmable gate arrays (FPGAs) and other logic devices, are realizing substantial problems in connecting external devices to the specified logic devices. For example, some logic devices are now being manufactured with a pin count that approaches 1500. In the future, pin counts could easily double. Even with just 1000 pins, however, require a substantial “breakout” area to couple the pins to the external devices. As the pin counts increase, the required breakout area size increases leading to larger and more expensive boards.
What is needed, therefore, is an apparatus and method that provide reducing pin counts for a specified logic device to reduce the immediate breakout area size and to reduce overall board complexity, size and cost.